What Is HBM? The Memory Chip Running the AI Boom, Who Makes It, and Why It Is the Crux of the Whole Selloff

TL;DR

• HBM stands for High Bandwidth Memory. It is ordinary DRAM stacked vertically into towers and wired to the processor through a massively wider connection. It delivers roughly 5 to 10 times the bandwidth of standard graphics memory.
• Every serious AI accelerator uses it. HBM3E sits on Nvidia's H200, B200 and B300 and AMD's MI355X. HBM4 is the current generation ramping for Nvidia's Vera Rubin platform.
• Three companies make it: SK Hynix, Samsung and Micron. SK Hynix has led with roughly 57% to 62% share, though forecasts put it nearer 50% in 2026 as Samsung climbs from about 20% toward 28%.
• All three are sold out for 2026. HBM is sold on long-term contracts, not spot. SK Hynix now has 10 contracted customers. That is the structural change that turned memory from a hog cycle into something that looks briefly like a subscription business.
• This matters right now because the entire bear case runs through one distinction: China's CXMT threatens commodity DRAM. It does not, yet, threaten HBM. Whether you believe that separation holds is the whole Korean crash in one question.

What Is HBM?

The short answer: HBM is DRAM that has been stacked into a tower and given a much wider road to the chip, so an AI processor can be fed data fast enough to keep it busy.

That is it. There is no exotic new physics. It is the same memory cells you have in your laptop, arranged in three dimensions and connected differently, and that rearrangement is worth tens of billions of dollars a quarter.

The Board

Three suppliers, one product, and an entire equity market's worth of argument sitting on top of it.

Why Stacking Solves the Actual Problem

AI training and inference are memory-bandwidth-bound, not compute-bound. That sentence is the reason HBM exists, and most coverage skips it.

A modern GPU can do arithmetic far faster than anyone can deliver numbers to it. Put a fast processor next to slow memory and the processor spends most of its life waiting. You have not built a supercomputer, you have built an expensive queue.

Traditional memory sits flat on a board, some distance from the chip, talking through a relatively narrow connection. The bottleneck is not how fast the cells are. It is how many wires you can physically run between the memory and the processor.

HBM attacks exactly that:

• Stack the dies vertically and connect them with through-silicon vias, holes drilled straight down through the silicon. Short vertical wires instead of long horizontal ones.
• Put the stack right next to the processor on the same package, so the distance signals travel collapses.
• Widen the road enormously. A single HBM3E stack talks over a 1,024-bit interface. Consumer memory works in tens of bits.

Shorter wires and a wider road also mean less power per bit moved, which matters when a data centre's real constraint is the electricity bill.

HBM3E vs HBM4: What Actually Changed

• Interface width per stack: 1,024-bit on HBM3E, 2,048-bit on HBM4. The doubling is the headline.
• Channels: 16 on HBM3E, 32 on HBM4.
• Per-pin data rate: roughly 9.6 Gbps on HBM3E, roughly 10 to 13 Gbps on HBM4 depending on vendor.
• Per-stack bandwidth: around 1.2 TB/s on HBM3E, well above that on HBM4, driven mostly by the doubled width rather than by faster pins.
• Shipping on: HBM3E runs Nvidia's H200, B200 and B300 and AMD's MI355X. HBM4 is for Nvidia's Vera Rubin platform.

The headline change is the doubled interface width. HBM4 is not primarily faster memory, it is twice as many lanes. That is why per-stack bandwidth jumps even though per-pin speeds only improve modestly.

Vendor specifics, because the competitive fight lives in the detail:

• SK Hynix completed HBM4 development claiming 10 Gbps and a 40% power efficiency improvement.
• Samsung's HBM4 runs 11.7 Gbps, above the 8 Gbps standard, and the company says it can push to 13 Gbps. Its HBM4E targets 16 Gbps per pin and 4.0 TB/s.
• Micron has sampled HBM4 at up to 11 Gbps and is working with foundry partners on HBM4E.

Note the awkward fact buried there: on raw published specs, Samsung's HBM4 is not the slow one. Market share and qualification timing, not silicon, have been its problem.

Who Makes HBM, and Who Is Winning

Three companies. That is the entire supply base for the most important component in AI infrastructure.

SK Hynix has been the leader throughout, holding roughly 62% of HBM through 2025 and around 57% by the fourth quarter. Forecasts put it near 50% in 2026. It reportedly secured close to two-thirds of Nvidia's HBM4 orders for Rubin, and its dominance here is why its Q2 earnings miss mattered enough to halt an entire national market twice.

Samsung is the comeback story. It stumbled badly on HBM3 packaging and Nvidia qualification, fell behind Micron in 2025 with roughly 17% share, and is now climbing: bit share forecast to rise from about 20% in 2025 to 28% in 2026, with an estimated 25% to 30% of Nvidia's Vera Rubin HBM4 volume. Its Q2 segment detail lands July 30.

Micron is the US option and the quiet winner of 2025, overtaking Samsung to take roughly 21% share, with about 20% of Nvidia's HBM4 allocation. It also runs the highest operating margin in the industry.

On June 5, 2026, Nvidia's Jensen Huang confirmed all three had passed HBM4 certification. Read that as the end of single-sourcing, and therefore as the beginning of price competition, which is a large part of what the market is currently repricing.

Why HBM Broke the Old Memory Business Model

Memory was historically the worst business in semiconductors. Commodity product, brutal capex, and a boom-bust cycle so reliable people set their watches by it. You built capacity into a shortage, the shortage ended, prices collapsed, everyone lost money, repeat.

HBM changed three things:

It is contracted, not spot. SK Hynix reported 10 long-term supply agreements in Q2. Customers book capacity years out because being short HBM means an idle GPU cluster, which is far more expensive than overpaying for memory.

It consumes disproportionate capacity. An HBM stack eats far more wafer area than the equivalent standard DRAM, so capacity diverted to HBM tightens the commodity market too. The AI boom squeezes the memory in your phone.

It carries real technical moat. Stacking, through-silicon vias and packaging yields are hard. Samsung, a company with essentially unlimited resources and decades of memory expertise, spent years failing to qualify. That is the clearest evidence available that this is not a commodity.

The result showed up in SK Hynix's Q2: a 76% operating margin and DRAM average selling prices up about 30% quarter over quarter. Memory companies did not use to print numbers like that. Ever.

Why HBM Is the Crux of the Entire Selloff

Now connect it to the tape, because this is why the explainer matters this week rather than in the abstract.

The bear case that has taken the Kospi down 39.7% from its June record has two engines: CXMT, which raised about $8.6 billion and debuted up 466% in Shanghai, and reports of Chinese domestic lithography reaching roughly 5 machines in 2026 and 20 in 2027.

Both of those aim at commodity DRAM and 28nm-class production. Neither is close to HBM4, which needs advanced packaging, stacking yield and a Nvidia qualification that took Samsung years to obtain.

So the bull and bear cases reduce to a single question:

• If the separation holds, HBM is a protected, contracted, high-margin business, the China threat compresses only the commodity half of the market, and the current de-rating has overshot badly.
• If the separation erodes, commodity DRAM oversupply drags the whole complex's pricing down, HBM margins normalise toward something ordinary, and the multiples people paid in June were fantasy.

Nothing in July's news moved an HBM roadmap. What it moved was the market's confidence that the wall between the two halves is permanent. Our running scorecard on that question sits in the memory supercycle thesis check.

Can You Buy HBM Stock?

There is no pure-play HBM company. You get exposure through diversified memory manufacturers, which means buying a lot of other things alongside it.

• MU (Micron) is the cleanest US-listed exposure: deep options chain, mature liquidity, no ADR wrapper, and the highest operating margin in the group. Our valuation work is in the MU and SNDK breakdown.
• SKHY (SK Hynix ADRs) is the highest-purity HBM bet available on a US exchange, and it carries a problem most buyers do not know about: the ADR trades roughly 22% above the Seoul shares, explained in full in the ADR premium piece.
• Samsung has no practical US-listed instrument. The OTC line is thin and has no usable options chain, so EWY, the Korea ETF, is the realistic proxy, at index weights and therefore diluted.
• The equipment layer, ASML and the packaging suppliers, sells to all three manufacturers regardless of who wins share. It is the pick-and-shovel version, and it sold off just as hard in July, which is either an error or a warning depending on your view.

One practical constraint worth naming: several of these names now carry share prices and implied volatilities that make single options contracts unwieldy for ordinary accounts. A contract controls 100 shares, so a $1,000 stock is $100,000 of notional per contract, which puts covered calls and cash-secured puts out of reach for most people and leaves debit spreads as the only structure that fits. That is a sizing fact, not a strategy preference.

The One-Line Read

HBM is DRAM stacked into towers and wired to the processor through twice the lanes, it exists because AI chips starve without it, three companies on earth can make it and all three are sold out through 2026, and the reason a Korean index fell 39.7% in five weeks is that the market stopped being certain the wall between this protected product and ordinary commodity memory will hold as long as everyone had assumed.